IBM, Oak Ridge and AMD open a shared testbed for quantum error correction

What was announced

On 5 November 2026 IBM, AMD and the Quantum Science Center, a Department of Energy research centre led by Oak Ridge National Laboratory (ORNL), announced a co-design platform for quantum error correction. The first deployment is at IBM's site in Poughkeepsie, New York, and the partners say it will also connect to the Oak Ridge Leadership Computing Facility in Tennessee.

The quantum side is IBM's Nighthawk, a 120-qubit superconducting processor whose qubits are connected in a square lattice; IBM's blog names the revision as Nighthawk r2. The classical side is ORNL's Umbra system, built on AMD Instinct MI355X GPUs and 5th Gen AMD EPYC CPUs. Neither the release nor IBM's blog gives node counts.^[1,2,3]

Why error correction needs a classical computer next door

An error-corrected quantum computer spreads each logical qubit over many physical qubits and repeatedly measures checks that reveal errors without disturbing the stored information. A classical decoder must turn each round of check results into a correction, and some operations, such as conditional gates, must wait for those answers. If the decoder is slow, errors pile up faster than they are removed.

That is why the partners stress co-location. IBM says researchers can measure qubits during a calculation, act on the results in real time, and work directly with the raw measurement signals. The stated aims are to test and train decoders on GPUs, compare what different error-correction methods cost in qubits, time, samples and classical computing, and find where GPU acceleration helps most.^[1,2,3]

Where it fits in IBM's and DOE's plans

IBM says the work will inform Starling, the fault-tolerant computer it plans to deliver by 2029, and research on hierarchical codes, which nest one code inside modules and another across them. The release links the platform to DOE's Genesis Mission, whose Quantum Genesis initiative, announced in June 2026, aims at machines with logical qubits numbering in the low hundreds in 2028.

DOE's Q Competition, published in September, offers up to $215 million: a $100 million pool shared among teams that demonstrate a first-generation machine with at least 100 logical qubits, and two bonus pools of up to $50 million for 150 and 200 logical qubits. DOE describes the goal as systems capable of hundreds of millions of fault-tolerant operations. The partners' release frames the same target as 100 logical qubits running 100,000 hard operations by late 2028.

Against that target the release cites IBM experiments with up to 70 logical qubits and 438 hard operations, and says the gap is roughly a 230-fold increase. The 70-logical-qubit run is the sampling experiment IBM and the University of Chicago reported in July 2026, which press coverage described as 2,415 logical two-qubit operations and 468 logical T gates; the release does not explain how its 438 figure is counted.^[1,2,4,5,6]

How to read it

This is research infrastructure, not a demonstration. The announcement gives no latency figures, no error rates and no logical-qubit results for the platform itself, and coverage so far, including SiliconANGLE's, relies on statements by the three partners. The useful test will be what comes out of it: published decoder latencies, measured logical error rates, and comparisons of error-correction schemes on real hardware with the classical cost counted.^[1,2,3]